A programmable integrated circuit, is a class of integrated circuits for which the logic function is defined by the customer using development system software after the IC has been manufactured and delivered to the end user. For example, one type of programmable integrated circuit, a field programmable gate array (FPGA), is an integrated circuit chip that includes programmable interconnect circuitry for interconnecting programmable components such as configurable logic blocks (CLBs), programmable input/output buffers (IOBs), and block random access memory (BRAMs). The CLBs include a number of function generators that can be configured as look up tables (LUTs), random access memories (RAMs), read-only memories (ROMs) or shift registers. Although the term LUT is referenced hereafter, any type of function generator may be used instead of a LUT. LUTs are typically made up of components such as multiplexers and static random access memory (SRAM) configuration memory cells. These SRAM memory cells can be programmed to configure the logic in the LUTs. Each LUT implements a logic function depending on how the SRAM memory cells are programmed or configured. A few of the possible logic functions that a LUT can implement are: AND, OR, and XOR gates. LUTs can be programmed to perform other functions such as an adder, multiplier, or shift register.
Classical methods of testing for bridge faults or shorts in the interconnect of FPGA devices involves driving one net of the interconnect at a time to one binary value and all other nets to the opposite binary value. A net forms an electronic connection between components. It can also form a connection from a single component to an IOB. A bridge fault is a short circuit between two nets. If the loads on the nets are observed to have different than expected values, then shorts are present in the device. A device tester is used to run test patterns and observe the net loads. Examples of device testers are the Teradyne J750 or Teradyne FLEX. By repeatedly dividing the nets into smaller groups, shorted nets are detected. This takes a long test time and requires multiple test configurations. The number of nets that need to be tested in order to provide realistic bridge fault coverage can be reduced by analyzing the physical layout and finding which resources can be “short candidates.” This analysis, however, can also take a long time.
What is needed is a way to test bridge faults in the interconnect of programmable integrated circuits such as FPGAs, quickly and comprehensively, and without multiple configurations of the programmable integrated circuit.